This blog is co-authored by Gordan Markuš, Canonical and Kumar Sankaran, Ventana Micro Systems

Unlocking the future of semiconductor innovation 

RISC-V, an open standard instruction set architecture (ISA), is rapidly shaping the future of high-performance computing, edge computing, and artificial intelligence. The RISC-V customizable and scalable ISA enables a new era of processor innovation and efficiency. Furthermore, RISC-V democratizes innovation by allowing new companies to develop their own products on its open ISA, breaking down barriers to entry and fostering a diverse ecosystem of technological advancement. 

By fostering a more open and innovative approach to product design, the RISC-V technology vendors are not just a participant in the future of technology; they are a driving force behind the evolution of computing across multiple domains. Its impact extends from the cloud to the edge:

• In modern data centers, enterprises seek a range of infrastructure solutions to support the breadth of modern workloads and requirements. RISC-V provides a versatile solution, offering a comprehensive suite of IP cores under a unified ISA that scales efficiently across various applications. This scalability and flexibility makes RISC-V an ideal foundation for addressing the diverse demands of today’s data center environments.
• In HPC, its adaptability allows for the creation of specialized processors that can handle complex computations at unprecedented speeds, while also offering a quick time to market for product builders.  
• For edge computing, RISC-V’s efficiency and the ability to tailor processors for specific tasks mean devices can process more data locally, reducing latency and the need for constant cloud connectivity. 
• In the realm of AI, the flexibility of RISC-V paves the way for the development of highly optimized AI chips. These chips can accelerate machine learning tasks by executing AI centric computations more efficiently, thus speeding up the training and inference of AI workloads.

One of the unique products that can be designed with RISC-V ISA are chiplets. Chiplets are smaller, modular blocks of silicon that can be integrated to form a larger, more complex chip. Instead of designing a single monolithic chip, a process that is increasingly challenging and expensive at cutting-edge process nodes, manufacturers can create chiplets that specialize in different functions and combine them as needed. RISC-V and chiplet technology is empowering a new era of chip design, enabling more companies to participate in innovation and tailor their products to specific market needs with unprecedented flexibility and cost efficiency.

Ventana and Canonical partnership and technology leadership

Canonical makes open source secure, reliable and easy to use, providing support for Ubuntu and a growing portfolio of enterprise-grade open source technologies. One of the key missions of Canonical is to improve the open source experience across ISA architectures. At the end of 2023, Canonical announced joining the RISC-V Software Ecosystem (RISE) community to  support the open source community and ecosystem partners in bringing the best of Ubuntu and open source to RISC-V platforms. 

As a part of our collaboration with the ecosystem, Canonical has been working closely with Ventana Micro Systems (Ventana). Ventana is delivering a family of high-performance RISC-V data center-class CPUs delivered in the form of multi-core chiplets or core IP for high-performance applications in the cloud, enterprise data center, hyperscale, 5G, edge compute, AI/ML and automotive markets. 

The relationship between Canonical and Ventana started with a collaboration on improving the upstream software availability of RISC-V in projects such as u-boot, EDKII and the Linux kernel. 

Over time, the teams have started enabling Ubuntu on Ventana’s Veyron product family. Through the continuous efforts of this partnership Ubuntu is available on the Ventana Veyron product family and as a part of Ventana’s Veyron Software Development Kit (SDK).

Furthermore, the collaboration extends to building full solutions for the datacenter, HPC, AI/ML and Automotive, integrating Domain Specific Accelerators (DSAs) and SDKs, promising to unlock new levels of performance and efficiency for developers and enterprises alike. Some of the targeted software stacks can be seen in the figure below.  

Today, Ventana and Canonical collaborate on a myriad of topics. Together through their joint efforts across open source communities and as a part of RISC-V Software Ecosystem (RISE), Ventana and Canonical are actively contributing to the growth of the RISC-V ecosystem. We are proud of the innovation and technology leadership our partnership brings to the ecosystem. 

Enabling the ecosystem with enterprise-grade and easy to consume open source on RISC-V platforms

Ubuntu is the reference OS for innovators and developers, but also the vehicle to enable enterprises to take products to market faster. Ubuntu enables teams to focus on their core applications without worrying about the stability of the underlying frameworks. Ventana and the RISC-V ecosystem recognise the value of Ubuntu and are using it as a base platform for their innovation. 

Furthermore, the availability of Ubuntu on RISC-V platforms not only allows developers to prototype their solutions easily but provides a path to market with enterprise-grade, secure  and supported open source solutions.Whether it’s for networking offloads in the data center, training AI models in the cloud, or running AI inference at the edge, Ubuntu is an established platform of choice.

Learn more about Canonical’s engagement in the RISC-V ecosystem 

• Linux made easy on RISC-V with Ubuntu 
• Demo: The Future of Ubuntu on RISC-V – Gordan Markus, Canonical 
• Download Ubuntu for RISC-V Platforms 
• Ubuntu continues expanding RISC-V enablement in 2022
• Silicon Programme | Partners 

Contact Canonical to bring Ubuntu and open source software to your RISC-V platform.

Learn more about Ventana

• http://www.ventanamicro.com

In essence, High Performance Computing (HPC) is quite simple. Speed and scale. In practice, the concept is quite complex and hard to achieve. It is not dissimilar to what happens when you go from a regular car to a supercar or a hypercar – the challenges and problems you encounter at 100 km/h are vastly different from those at 300 km/h. A whole new set of constraints emerges.

Furthermore, no two HPC setups are the same. Every organisation does HPC in a manner uniquely tailored to their workloads and requirements. That said, the basic components and functions are repeatable across the entire spectrum of tools and technologies used in this space. Today, we’d like to share our recipe on how you can best blend these “ingredients” to build a Canonical-flavoured HPC setup. We do not see it as an absolute truth or the one superior way of doing things – but we believe it is practical, pragmatic and efficient.

What makes HPC … HPC?

At the hardware stratum, the power of HPC will usually come from parallelised execution of discrete chunks of data on relatively inexpensive commodity machines – relative to what the cost would be if there was a single system that could offer the same kind of performance. The use of GPU modules can make data crunching significantly faster compared to conventional CPUs, which is why HPC setups will often include graphics cards for processing.

The parallel execution needs to be fast – and well orchestrated – to avoid starvation at any one point in the setup. To that end, HPC setups will also include fast network and fast storage, to minimise (or eliminate) the gap in the data transfer and processing speed provided by conventionally fast elements (CPU/GPU, memory) and slow elements (I/O bus).

On the software level, orchestration will require an intelligent scheduler, which can process, dispatch and manage data across the HPC setup (a cluster of compute nodes). Usually, engineers and scientists working with the data will also require some programs to feed their workloads into the HPC environment. To that end, they will need a console to dispatch their jobs, and a set of tools and utilities to prepare their jobs – best if they can be managed centrally through a package manager.

In a rather recipe-like style, HPC boils down to: a set of machines with CPU/GPUs, fast storage, fast network, scheduler, package manager, and a management console. Now, let’s talk about what you could expect from Canonical in the HPC space.

Juju for hardware deployment

If you’ve never heard of Juju, here’s a one-liner: Juju is an open source orchestration engine for software operators that enables the deployment, integration and lifecycle management of applications at any scale, on any infrastructure.

The idea is that rather than spending a LOT of time figuring out how to build the topology of your data centre or cloud or HPC setup, you let Juju build the environment for you, and you invest time in the actual workloads you want to run. Of course, there are no shortcuts, and Juju isn’t a magical solution for IT-less IT. But it can perhaps help, in some scenarios, get businesses and organisations past the initial hurdle of setting up an environment.

Juju’s combination of deployment and operations behaviour comes in the form of charms – these are operators – business logic encapsulated in reusable software packages that automate every aspect of an application’s life. In other words, charms are packages that bundle both the configuration and application business logic (how it should work once deployed). Therefore, for HPC, there could be a Charmed HPC solution. It will include the deployment component, as well as the software ingredients needed to run a fully self-contained, independent HPC setup.

A set of charms and snaps

Once you move past the hardware hurdle, the software part should become easier. Juju will provision Ubuntu systems, complete with all the bits and pieces needed to do HPC workloads right away.

Spack will be the package manager (as we mentioned in our holidays message). It allows HPC users to quickly and easily search and install some 7,000 scientific programs and utilities. Next, once the engineers and scientists are ready to dispatch their workloads, they can use the Open OnDemand utility to connect to the HPC cluster.

From there on, SLURM will process the tasks and schedule them across the cluster. Canonical aims to provide software and hardware optimisation at every junction, so when different processes run on a Canonical HPC cluster, the end user will benefit from better performance, power utilisation, and improved security and stability. In due course, we will share more details on how we intend to achieve this, as well as provide timely updates on benchmarks and tweaks.

There will also be an observability component to help monitor the environment, which for now will remain unnamed. We also think strong integration with LDAP and NFS is a must for such a setup to work well, so we will invest time in providing those, too. Ceph integration is another component in our recipe.

This is a recommendation, not a rule

By and large, this is our “dish”. But, like any dish, it can always benefit from more seasoning. We will figure out those fine details as we go along, and that may include additional software components we haven’t mentioned above. Nevertheless, we want to build our HPC solution to be flexible and modular, so if you have specific requirements, it doesn’t become a take-it-or-leave it product. 

It’s still early days in how we want to conceive and build our solution, so you should stay tuned for updates. The easiest way is to subscribe to the newsletter, or reach out directly if you have questions..

Take care, and watch out for the next instalment in this series.

Photo by Katie Smith on Unsplash.